Integrated circuit I/O pad cell modeling

ABSTRACT

A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells of all types, and the interaction of external pull cells/resistors with pad cells of all types. This modeling technique involves the use of three separate pins on each bi-directional pad cell: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources. The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells. The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. The existing pad pin serves as the input-only pin. The model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations.

TECHNICAL FIELD

[0001] The present invention relates to modeling of electrical circuitcharacteristics, and more specifically to modeling of an integratedcircuit I/O or bi-directional pad cell.

BACKGROUND OF THE INVENTION

[0002] The design of integrated circuits has become increasingly complexas more and more circuits are realizable on a given substrate. Thisincrease in circuit density, and resulting increase in circuitfunctionality, has resulted in the need for automated circuit designtools. These circuit design tools (hereinafter design test tools) assista circuit designer in logic entry, simulation and test patterngeneration.

[0003] Simulation of integrated circuit designs generally rely onmodels, or other types of information, that the simulator uses togenerate signals resulting from some type of circuit stimulus. Therelative timings between the stimulus and resulting response are ofcritical importance as circuits are operated at high speed.

[0004] Also of particular importance is how well the simulated responsesactually track with the resulting physical implementation of thecircuit. This correspondence between predicted and actual responses isimportant both as to the logical circuit design itself, and to the testpatterns that are generated to test the resulting circuit embodiment.Incorrect timings of the logical circuit could result in logical errorsbeing propagated into the physical embodiment of the integrated circuit.Incorrect timings for test patterns could result in test patterns beinggenerated (stimulus and expected response) which don't match the actualcircuit responses during test.

[0005] The modeling and simulation of integrated circuit input andoutput (I/O) pins is particularly troublesome, in that due to thebi-directional nature of many I/O pins (such as those driving andreceiving signals on a bus), there can be contentions where more thanone driver is trying to drive a given I/O signal to a given (andsometimes conflicting) voltage level. When contention situations exist,the simulation results are erroneous, due to the inability to determinewhich direction the signal is to be propagated (e.g. into the chip, asdriven from some external source, or out of the chip, as driven by thechip circuitry itself).

[0006] Current methods of utilizing I/O enable signals for directiondetermination do not provide actual switch point locations, and do notidentify when contention is occurring. These limitations are becomingincreasingly important for designs which run at higher frequencies andthose which require I/O contention situations to exist.

[0007] Enhanced modeling of both internal pull cells and external pullresistors is necessary to improve simulation accuracy as well as toinsure that design test tools can extract appropriate test vectors forsignals which utilize pull cells/resistors. Incomplete and/or inaccuratepull-up/down information can result in incorrect simulationfunctionality as well as misplaced strobing (i.e. checking the value) ofresistive states. These issues have repeatedly caused manufacturing testproblems over the past several years.

[0008] Using the combination of the I/O enable signal and the resolvedI/O signal for design analysis does not provide enough information toproperly handle mid-cycle I/O capabilities and contention situations.

[0009] In the case of resistive state modeling, current techniquesprovide less than accurate simulation information. In some cases, thistype of inaccuracy compromises the correctness of the designfunctionality exhibited during simulation. It also makes strobing ofresistive states difficult during manufacturing tests.

SUMMARY OF THE INVENTION

[0010] It is an object of the present invention to provide an improvedcircuit model for simulation of electrical circuits.

[0011] It is another object of the present invention to provide animproved I/O pad cell model for use by a simulator.

[0012] It is yet another object of the present invention to provideaccurate timing information in the generation of test patterns for anintegrated circuit.

[0013] A design system for modeling bi-directional pad cells, theinteraction of internal pull cells/resistors with pad cells, and theinteraction of external pull cells/resistors with pad cells is provided.A new modeling technique, referred to herein as split-I/O modeling,involves the use of three separate pins on each bi-directional pad cellmodel: an input-only pin, an output-only pin, and a resolved pin. Theinput-only pin reflects the data that is supplied to the pad fromexternal sources (strong data that is forced in). The output-only pinreflects the data that is supplied as output from the pad cell (strongdata from the output driver). The resolved pin reflects the combinationof the input and the output data that are present, as well as the effectof resistive data supplied by pull-up/down resistors/cells (i.e. theresistive state).

[0014] The output-only and resolved pins are implemented as internal orhidden pins within a pad cell model. These pins are included in themodel for the I/O pad cells in a given library. These pins are namedO_ONLY (the output-only pin) and RESOLVED (the resolved pin). Theexisting pad pin serves as the input-only pin. The system is able toinstruct the simulator to log the internal signals through the use ofthe occurrence name for each I/O pad cell.

[0015] The split I/O model provides two modes of operation such that thesame model can be used for either chip-level or system-levelsimulations.

BRIEF DESCRIPTION OF THE DRAWING

[0016]FIG. 1 shows sample bi-directional waveforms.

[0017]FIG. 2 shows an example of I/O contention.

[0018]FIG. 3 shows a modified bi-directional pad and pull-upcombination.

[0019]FIG. 4 shows an alternate bi-directional pad with pull leaf cell.

[0020]FIG. 5 shows an I/O pad with internal pull-up.

[0021]FIG. 6 shows the resulting waveform for the I/O pad of FIG. 5.

[0022]FIG. 7 shows an I/O pad with external pull-up.

[0023]FIG. 8 shows the resulting waveform for the I/O pad of FIG. 7.

[0024]FIG. 9 shows a waveform for resistive state modeling for a SCSIpad cell.

[0025]FIG. 10 shows a design methodology for designing and fabricatingintegrated circuit devices.

[0026]FIG. 11 shows interdependencies for logic simulation of anintegrated circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0027] In the design of integrated circuits, including applicationspecific integrated circuits (ASICs), there are numerous types of designtest tools available to assist the logic designer in logic entry,simulation, layout, test pattern generation, etc. These tools are wellknown in the art. The present invention is a model used to represent aparticular portion of an integrated circuit design, specifically the I/Opad cell. This model is used in conjunction with a simulator tosynthesize the behavior of an actual I/O pad cell when embodied as partof a resulting integrated circuit.

[0028]FIG. 10 shows a typical design methodology for designingintegrated circuits, and in particular for designing ASICs. First,initial planning of the design is done at 90. The design is then enteredat 91 using standard CAE/CAD tools known in the industry, such as thosefrom Cadence Design Systems, Mentor Graphics, Synopsis and Viewlogic.Part of logic entry includes compiling the pad cells, using an I/Ocompiler such as the VS500 I/O Compiler, available from AT&T GlobalInformation Solutions Company, Microelectronics Division located in Ft.Collins, Colo. (hereinafter AT&T MPD). After design entry, the user canoptionally perform static timing analysis at 92 (using a tool such asVeriTime, available from Cadence Design Systems, Inc. which is locatedin San Jose, Calif.), as well as generate input stimulus waveforms at 93for use in subsequent simulation (using a tool such as Wisil, alsoavailable from AT&T MPD). After such stimulus waveform creation, theuser can optionally perform functional simulations at 94. The user thenperforms real time simulation at 95 using the same simulator. Thesesimulation steps are where the present invention is utilized. Theparticular model detailed herein was written for use with the Verilogsimulator, such simulator being available from Cadence Design Systems.After simulation, power analysis can optionally be performed at 96 usinga PowerCalc tool, available from AT&T MPD. The simulation results arethen validated at 97, preferably with the Verify design test tool (alsoavailable from AT&T MPD). A net checking tool called NetChecker (alsoavailable from AT&T MPD) can then be run at 98. The layout 99,post-layout verification 100 and prototype 101 phases shown in FIG. 10Care standard in the industry, and are not important to the understandingof the present invention described herein.

[0029] As mentioned above, logic simulators are commonly known in theindustry, and such simulators are provided by companies such asViewlogic, Cadence, Mentor Graphics, Zycad and Ikos. These simulatorsnot only provide for device-level simulation, but also allow forbehavior-model simulation. With behavior-model simulation, a particularsubset of the integrated circuit to be simulated is replaced with aprogramming model that generates output responses to various inputstimuli.

[0030] The split I/O pad cell model described herein adheres to standardbehavior-model interface protocols/programming interfaces known in theindustry. Accordingly, the design techniques used for the model itselfwill be described herein, with the specific implementation for theVerilog simulator being listed thereafter. It is a matter of routinecoding to adhere to the techniques described herein to generate specificmodels for other types of simulators.

[0031] In the following discussions, logic states will be referred to bythe appropriate state characters. The list of state characters that areused, and the logic state/strength combination that they represent, areshown in Table 1. TABLE 1 State Characters State Character Logic LevelStrength 0 low strong 1 high strong X unknown strong L low resistive Hhigh resistive R unknown resistive Z unknown high-impedance

[0032] Waveform diagrams are used to provide examples of the desiredmodel behavior. Table 2 shows the types of lines used in the waveformdiagrams to represent each of the different strengths. TABLE 2 WaveformStrengths strong ——— resistive - - - - - high-impedance ...........

[0033] To illustrate the signals present on the input-only, output-only,and resolved pins, consider the waveforms in FIG. 1. This example showsa situation where the I/O pin is first in input mode, as indicated at20, with a logic one being driven from an external source. The I/O thenswitches to an output mode, as indicated at 22, with a logic zero thenbeing driven from the pad cell. The resolved signal is the resultingsignal value as determined by the simulator, based upon the input-onlyand output-only signals. An enable signal (not shown) is ‘active’ duringthe region 22 of outputting data, and ‘inactive’ during the region 20 ofinputting data. Note that in this example, use of the I/O enable signalin combination with the resolved signal 24 would have been sufficient todetermine which portion of the resolved waveform represented input dataand which represented output data.

[0034] However, consider the waveforms shown in FIG. 2. This exampleshows an I/O contention situation which illustrates the need for usingthe input-only and output-only signals. Initially, the I/O pin is ininput mode, as shown at 24, with a logic one being driven by an externalsource. Then, the I/O switches to an output mode, as shown at 26, with alogic one being driven by the pad cell. This results in a contentionsituation, as both the input and output signals are attempting to drivethe signal to a logic one. The resolved signal does not reflect theturning on of the output signal, and remains at a logic one until boththe input and output are at high impedance, as indicated at 28.

[0035] While, in this case, the use of an I/O enable signal wouldprovide an approximate indication of the time at which the output turnedon and off, it would not indicate the precise turn-on and turn-offtimes, due to an internal delay between the time the enable signal isdetected by input circuitry and the time the resulting output signal isactually asserted. When dealing with low speed designs, the delaybetween the I/O enable transition and the actual turn-on/off times isnegligible. However, for high speed circuits it becomes significant: theexact location of the I/O switch point must be determined. Theoutput-only signal provides this exact information concerning theturn-on/off points. This is why use of the output-only signal isnecessary.

[0036] As mentioned above, use of an I/O enable signal provides someindication of the output turn-on/off times. And, the output-only signalcompletes the picture of the data that is provided by the I/O pad cellitself. However, neither the I/O enable signal, output-only signal, orthe resolved signal provide an indication of the time at which the inputdata turned off. Since the tester must be programmed to produce theinput waveform that was applied as stimulus during simulation, thedesign test tools need to determine the exact input waveform that wasapplied. More information is needed to make this determination. Theinput-only signal provides this information. This is why use of theinput-only signal is necessary.

[0037] While the input-only and output-only signals will provide thedesign test tools with sufficient information to both determinedirectionality and determine turn-on/off times, only the resolved signalcontains information regarding the signal that results from mixing theinput-only signal, the output-only signal, internal pull cells (if any)and external pull resistors (if any). Since the resolved signal is theonly signal that properly reflects the contribution of the resistivecomponents, it must also be provided in each I/O pad cell model to allowthe design test tools to have a complete picture of the state of thebi-directional signal. As a result, the input-only, output-only andresolved signals are included in the simulation output file for eachbi-directional pad cell in the design.

[0038] The bi-directional pad cell models operate in two modes:tester-compatible mode and system simulation mode. The simsetup files'TESTER_EMULATION keyword is used to select which mode is in use for aparticular simulation. It should be noted that some simulators requirethe TESTER_EMULATION keyword to be entered as a parameter on the commandline when invoking the simulator. Setting TESTER_EMULATION on (either bysimsetup file or command invocation parameter) will imply use of thetester-compatible mode. In tester-compatible mode, the three pins of thebi-directional pad cell model provide the information described above.In system simulation mode, the isolation between the input-only and theresolved signal is removed and these two signals are equivalent. This isnecessary since other components may need to be connected to the pad pin(the input-only signal) in system simulations. This signal not onlyreflects what is going into the pad, but also reflects the output sothat the other component(s) connected to the pad can react to the pad'soutput. Because of this, simulation results that are generated in systemsimulation mode may not be used to generate test patterns formanufacturing test purposes. It should be noted that the term ‘reflect’as used herein means ‘to show’ or ‘to bring or cast as a result’, anddoes not mean ‘to throw back light or sound’ (see e.g. Webster's NewCollegiate Dictionary).

[0039] As mentioned earlier, each bi-directional pad cell model in eachlibrary provides the three required signals. The following sectionsdescribe two types of implementations. Note that in both cases, theoutput-only (O_ONLY) and the resolved (RESOLVED) pins are implemented asinternal pins that cannot be connected to other signals in the design.

[0040] As described above, there are two new signals that are requiredin every I/O pad cell in the cell libraries: an input-only signal and anoutput-only signal. These new signals are obtained by adding newcomponents to existing cell models known in the art. The preferredlibraries containing cell models are the VS500 library and non-VS500libraries, both of which are available from AT&T MPD.

[0041] In the non-VS500 libraries, all of the circuitry was added withinthe bi-directional pad cells themselves. FIG. 3 shows a modified padcell 30 in combination with an internal pull-up cell 32. Note that theinternal pull-up 32 is completely optional, but is shown here to clarifythat its connection 34 to the I/O pad cell is isolated from the outputdriver 36 by an isolation buffer 38 that has been added to the pad cellmodel (the isolation buffer does not actually exist in silicon). Itshould also be noted that although the example only shows one particularI/O pad cell in the non-VS500 libraries, the changes are applicable toall I/O pad cells in the non-VS500 library.

[0042] The existing I/O pad cell, prior to modification, comprises astacked p-channel and n-channel transistor pair output driver 36, and anI/O pad 48. Elements 38 and 40 within the pad cell 30 indicate newcircuitry that has been added. The circuitry 38 is an isolation bufferwhich insures that the output-only signal is not affected by any inputto the cell other than from the PCH/NCH pins 35 and 37. The receivercircuitry 40 is more complex. It contains an optional external pull-upresistor 42 whose presence and strength are controlled through keywordsin the simsetup file (see Table 3 below). It also contains someswitchable circuitry 43 that is controlled by the TESTER_EMULATIONkeyword in the simsetup file. The switchable circuitry selects either toisolate the input-only signal (switch down), or to directly connect theinput-only signal to the resolved signal (switch up). Intester-compatible mode, the buffer 44 is used to isolate the input-onlysignal from the resolved signal. In system simulation mode, the wire 46connects the input-only signal directly to the resolved signal to letdata flow in both directions.

[0043]FIG. 4 shows a second implementation, where a second type ofbi-directional pad macro (from the VS500 library) was modified toprovide the required signals. This second implementation has leaf cellswhich are connected by the I/O compiler to create bi-directional padmacros 50. There is an input leaf cell 52 and an output leaf cell 54. Apull leaf cell 56 is added if an internal pull-up, pull-down, or keeperis desired.

[0044] As in the first implementation, elements 38 and 40 are newcircuitry that has been added. Elements 38 and 40 are the same aspreviously described with respect to FIG. 3. The I/O compiler isresponsible for adding this circuitry between the leaf cells as itcreates the pad macro using the fixed signal names of O_ONLY for theoutput-only signal and RESOLVED for the resolved signal.

[0045] Internal pull resistor modeling will now be described. Forpurposes of this description, internal pull resistors are the pull-upand pull-down cells that can be connected to a pad cell and which lieinside the integrated circuit (IC), such as elements 32 of FIG. 3 and 56of FIG. 4. The interaction between these cells and the pad cells towhich they are connected has been a problem area in the past.

[0046] Situations have existed which allowed a signal to transitioninstantaneously from a strong state to a resistive state of the oppositepolarity (to transition, for example, from a strong logic zero state toa resistive logic one state). This behavior is not realistic and cancause two problems: incorrect input into the device and incorrect outputfrom the device. Each of these problems is discussed in more detailbelow. The combination of an I/O pad cell with an internal pull-up cellis used to illustrate these problems. This configuration is shown inFIG. 5.

[0047] The issue of incorrect input data applies only to input andbi-directional signals. To understand the potential problems that canarise, consider the following situation regarding the circuit of FIG. 5and related timing diagram of FIG. 6. If a strong logic zero state isbeing applied as input to the I/O pad 48 and is then taken away, thestimulus entering the pad transitions from a strong logic zero to ahigh-impedance state, as shown at 60 of FIG. 6. The internal pull-up 32(which, in this circuit, is always enabled) will then begin to pull thesignal to a resistive logic one state. However, this will take a finiteamount of time depending on the strength of the pull-up and the clockrate of the device. It could take as much as several clock cycles.

[0048] Assuming that the output side of the I/O pad is disabledthroughout this time, the data that is present on the DI pin 61 of theI/O pad is in transition from logic zero to logic one. Since the data onthe DI pin is potentially controlling internal logic, this transitionmust be modeled accurately. If it appears to reach a logic one state tooearly, the device's performance during simulation may differ from theactual performance of the resulting fabricated IC. Therefore, the modeltakes into account the strength of the pull resistor 32, as well as thecapacitive loading of the I/O pad 48, to determine the transition time.For external pull resistors, both the pull resistor cell's strength (interms of current source/sink) and the capacitive load value for each pinare available in the simsetup file and are used during simulation forthe necessary calculations. This applies to any transition from a strongstate to a resistive state of the opposite polarity. FIG. 6 shows thewaveforms which are produced on the pad cell's signals in thissituation.

[0049] Since it is not possible to model the actual waveform which isproduced by this type of transition, a suitable approximation isnecessary. To insure that the data is not utilized as valid input dataduring the transition region, it is necessary to model this portion ofthe waveform as having an unknown level. And, since any strong data thatis driven onto the pad during the transition region—either as input tothe pad or output from the pad—should take precedence over thistransitioning resistive data, it must have a resistive strength. Forthese reasons, a resistive unknown state (the format state ‘R’) is used,as shown at 62 of FIG. 6.

[0050] The issue of incorrect output data coming out of the deviceapplies only to output and bi-directional signals. The configurationshown in FIG. 5 and utilized in the previous section can also be used toillustrate this type of problem. If the transition from a strong logiczero state to a resistive logic one state occurs instantaneously, itwill appear to the design test tools as though the resistive data isavailable for strobing immediately. The resulting test vectors couldthen potentially attempt to strobe this resistive data while it is stillin transition (as mentioned earlier, the transition could actually spanseveral clock cycles). When this occurs, the device will fail duringtest. The test engineer must manually remove the strobing from the testvectors for each such occurrence. This type of manual effort is timeconsuming and must be avoided. The use of the ‘R’ state 62 during thetransition region, as shown in FIG. 6, will prevent strobing fromoccurring before the transition is complete.

[0051] External pull-up resistor modeling will now be described. Forpurposes of this description, an external pull-up resistor is one thatis connected to a pad cell but which lies outside the IC (as previouslynoted, these external pull-ups will now be part of the pad cell/macromodel), such as element 70 of FIG. 7. The interaction between theseexternal resistors and the pad cells to which they are connected hasbeen a problem area in the past. As with the case of internal pullcells, situations have existed that allowed a signal to transitioninstantaneously from a strong state to a resistive state of the oppositepolarity. This behavior is not realistic and can cause the same twoproblems that were previously described for internal pull cells. Thefollowing discussions use the combination of an I/O pad cell with anexternal pull-up resistor to illustrate these problems. Thisconfiguration is shown in FIG. 7.

[0052] The situations previously cited apply as well to external pull-upresistors as they do to internal pull cells. Therefore, the modeling ofthese situations must be almost identical to the modeling previouslyprescribed regarding internal pull transistors. The main difference isthat the presence and strength of the external pull-up 70 is controlledentirely through keyword(s) in the simsetup file, as shown below inTable 3.

[0053] As an example of this situation, consider the waveforms shown inFIG. 8. These waveforms begin with the I/O pad's output enabled anddriving a strong logic zero state at 80. When the output turns off at82, the resistive data from the external pull-up begins to pull the padto a resistive logic one state at 84. These waveforms show the desiredmodeling where the resolved state passes through the ‘R’ state. Again,the transition time is calculated by the model using the strength of thepull resistor and the capacitive loading on the pad.

[0054] The following describes several special case situations whichdeserve additional discussion:

[0055] 1) In some cases, SCSI (which stands for small-computer standardinterface, and which is a commonly known industry standard) pad cellsare used to drive clock signals which are unable to tolerate unknowninput states. For this reason, the modeling of resistive states inconnection to SCSI pad cells should be slightly different from that ofother I/O pad cells. In order to avoid using a resistive unknown (R)state on these signals, a technique is used which avoids the unknownstate usage while insuring that simulation functionality and strobeplacements for test purposes are not adversely affected. This techniqueinvolves utilizing resistive high (H) and low (L) states in place of theresistive unknowns, as shown in FIG. 9.

[0056] Note that the pull-up times vary greatly between the best- andworst-case simulations. Both simulations show the signal transitioningfrom a strong logic zero state to a resistive logic zero state L as theoutput driver turns off. For best-case, the signal transitions to apulled-up state H one simulation tick later. For worst-case, the signalstays at a resistive logic zero state until the maximum pull-up delaytime (calculated using the pull-up strength and the pin's capacitiveload). In a composite simulation (i.e. where the best case and worstcase timings are merged into a single simulation), the resultingwaveform will be such that the signal will transition to a resistivelogic zero state L for one tick, then to a resistive unknown state R forthe time up to the point where the signal reaches a resistive logic onestate H at the worst-case pull-up time.

[0057] 2) In the past, open drain configurations were treated as specialcases. In certain situations, a pull-up was assumed to be used incombination with open drain cells even if no pull-up was present in theschematic. However, in many cases, “normal” output and I/O cells couldbe configured as open drain cells by the user. These cells would notmake the same pull-up assumptions as the open drain cells. To avoid thissituation, and to insure that all of the output and I/O pad cells modelresistive states consistently, it is preferable to eliminate this typeof assumption. If a pull-up is desired, it will have to be specified bythe user (i.e. internal pull-up cells must be present in the schematicand external pull-up resistors must be specified in the simsetup file).This provides the user with complete control over whether resistivestates occur on open drain signals during simulation.

[0058] 3) The situation where the internal pull cell's enable signal istoggled during simulation is considered a special case. Whenever thepull cell becomes enabled, the model considers the current state of theresolved I/O signal to determine the proper action. If the resolvedsignal is already at the same logic level that the pull cell is tied to(logic one for pull-ups; logic zero for pull-downs), the output of thepull cell attains the resistive state at that level instantaneously. Ifthe resolved signal is at a strong state of the opposite polarity (logiczero for pull-ups; logic one for pull-downs), or if it is at a strongunknown state, the pull cell passes through the resistive unknown (‘R’)state for the calculated transition time on its way to the resistivestate of the opposite level (in a manner similar to that shown for thecomposite signal of FIG. 9).

[0059] 4) It is possible for the user to specify that both a pull-up anda pull-down exist on the same pad (these may be a combination ofinternal and external). If both the pull-up and pull-down are enabled atthe same time, and there is no strong signal present during this time,the resulting resolved state is a resistive unknown (‘R’) even if onepull cell is stronger than the other.

[0060] The following describes several impacts to users of the split I/Omodel:

[0061] 1) Users of bi-directional signals are affected by the split-I/Otechnique. The worst-case effect is that their simulation outputincludes the input-only and output-only signals for each bi-directionalpad cell occurrence in addition to the resolved signal. Each of thesesignals is utilized by the design test tools in analyzing the simulationresults. The I/O enable signal is no longer needed to be included in thesimulation output.

[0062] 2) Any user of internal pull cells or external pull-up resistorsis also affected by the modeling changes regarding generated resistivestate output values. This will occur regardless of whether the pullcell/resistor is used in conjunction with input, output, or I/O pads—themodeling changes will affect each type of pad. However, the use of pullcells/resistors will not require any changes to the way the userperforms the simulations. Users of external pull-up resistors arerequired to specify, in the simsetup file, which pads are connected toan external resistor and the strength (current sink/source rating) ofthe pull resistor. For libraries which support mixed voltages, the useris also required to specify the voltage level to which the externalpull-up is connected. Examples of this are shown below in Table 3.

[0063] The simulation setup (simsetup) file of Table 3 is arepresentative file which specifies various parameters andconfigurations for use with simulation. TABLE 3 # This sim.setup filecreated by ‘ncr_setup' # Version 11.0.0_1.5.0#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# ASIC Specific Information#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -DESIGN_NAME my_design TECHNOLOGY vs500 CHIP_VOLTAGE 5.0_onlyBOUNDARY_SCAN false#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Delay Information#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -#- - - - - - - - - - - - - - - - - - - - - - - # Best case operatingpoint #- - - - - - - - - - - - - - - - - - - - - - - BEST_VPT_NAME bestBEST_TEMP 0 BEST_VOLT 5.5 BEST_PROC b BEST_PARASITIC b#- - - - - - - - - - - - - - - - - - - - - - - # Typical case operatingpoint #- - - - - - - - - - - - - - - - - - - - - - - TYPICAL_VPT_NAMEtypical #OFF TYPICAL_TEMP 25 TYPICAL_VOLT 5.0 TYPICAL_PROC tTYPICAL_PARASITIC t #- - - - - - - - - - - - - - - - - - - - - - - #Worst case operating point#- - - - - - - - - - - - - - - - - - - - - - - WORST_VPT_NAME worstWORST_TEMP 70 WORST_VOLT 4.5 WORST_PROC w WORST_PARASITIC w#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Pull-Up Information#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# The following three lines define default pullup. If an # externalpullup is not specified [in sim.setup] for an OPEN # DRAIN, the defaultvalues will be used. DEFAULT_EXTERNAL_LOAD 30.0 DEFAULT_PULLUP_CURRENT0.0 DEFAULT_PULLUP_VOLTAGE 5 # The following three key-words(PULLUP_CURRENT, # PULLUP_VOLTAGE, and EXTERNAL_LOAD) are used tospecify # the rise time of the external pullup. In the example above, a# PAD is given a pullup that supplies 0.5 ma at 5 volts. PAD # is loadedwith 30.0 pf. PULLUP_CURRENT PAD 0.5 PULLUP_VOLTAGE PAD 5 EXTERNAL_LOADPAD 30.0#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Library Information#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -VITA_DATA_PATH .:/usr/local/ncr/MG_11.0.4/data_files/vs500 VITA_HEADER/usr/local/ncr/MG_11.0.4/data_files/vs500/vs500.vt5.head CELLCAP_DATA/usr/local/ncr/MG_11.0.4/data_files/vs500_DLM.cellcap#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Output Files Placed in ‘DESIGN_NAME/NCR_DESIGN’ directory#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -NCR_DESIGN_DIR ncr_design#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Cellcount output file: my_design.cellcount # Critpath output file:my_design.critpath # DVE output file: my_design.dve_setup # Netcheckeroutput file: my_design.netchecker # Design Vita file: my_design.vt5 #Node5rc output file: my_design.ndr # Port Occurrence file:my_design.portoccs#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -# Global Information#- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -CELLCOUNT off #Does ncr_presim run ncr_cellcount? NETCHECKER off #Doesncr_presim run ncr_netchecker? NODE5RC off #Does ncr_presim runncr_node5rc? SYNCRP_X_OUTPUTS on POR_DELAY 0.0 #Specify in nanosecondsESTIMATED_GATE_COUNT 0 ST_MARGIN 0.0 #Specify in nanoseconds HT_MARGIN0.0 #Specify in nanoseconds RT_MARGIN 0.0 #Specify in nanosecondsMPW_MARGIN 0.0 #Specify in nanoseconds TESTER_EMULATION #Specifying thiskey-word turns tester_emul on # Input Signal InformationDEFAULT_INPUT_RISE 5.0 DEFAULT_INPUT_FALL 5.0 # Output SignalInformation DEFAULT_MODULE_LOAD 0.0 #SKEW 0.0 #BA_FILE_LIST # Colonseparated list

[0064] The handling of external pullup information in the simsetup filewarrants further discussion. The strength of the pullup is specified inthe simsetup file, using the pullup_current and pullup_voltage keywordsas shown above in Table 3. If an external pullup is not specified or isgiven a strength of zero, and the cell is not an open drain, the effectis to remove the pullup. If the cell is an open drain, then the splitI/O model uses the default_current and default_voltage if thepullup_current and pullup_voltage are not specified (the only way toremove the external pullup from the open drain is to specify apullup_current or voltage as 0). The pullup delays are calculated byNode5RC.

[0065] Node5RC calculates the delay for the external pullup using thefollowing formula. This formula calculates the rise time from 0 to 1.5volts (threshold) using a resistive model. The RefVoltage andPullupCurrent are specified in the simsetup file using thepullup_voltage and pullup_current keywords. TABLE 4 External PullupDelay Calculation${tp} = {- \left( {{\log \left( {1 - \frac{1.5}{RefVoltage}} \right)} \cdot \frac{RefVoltage}{PullupCurrent} \cdot {ExternalLoad} \cdot 100} \right)}$

[0066] The following code listing in Table 5 is the split I/O modelsoftware code that is operational with a VeriLog simulator. Other typesof simulators may be used by adhering to the underlying principles andtechniques of this code, and description hereinabove, to the particularbehavioral programming language required for those particularsimulators. TABLE 5 Split I/O Pad Model Code Listing//******************************************************** //Copyright(c) AT&T Global Information Solutions 1994 moduleB0C1S310C11C(A,ENB,PAD,Z); output Z; inout PAD; input A, ENB;J0C1S0000000 IPAD(.PAD(RESOLVED), .Z(Z)); /*Input - Fig 4 #52 */U0000000C1IC OPAD(.A(A), .ENB(ENB), .PAD(O_ONLY)); /*Output - Fig 4 # 54*/ A00003100000 PULLINST(.VDDIN(1′b0), .PAD(RESOLVED));/*Pullup - Fig 4# 56*/ NCR_ISOLATE iso1(.X(RESOLVED),.A(O_ONLY)); /* Isolate - Figure 4# 38 */ NCR_EXTERNAL ext1(.VDDIN(1′b1),.PAD(RESOLVED)); /* External -Fig 4 # 42 */ NCR_SWITCH sw1(.X(RESOLVED),.A(PAD)); /* Switch - Fig 4 #43 and 44 */ endmodule//******************************************************** //Copyright(c) AT&T Global Information Solutions 1994

timescale 100ps/10ps

celldefine module J0C1S0000000(PAD,Z) input PAD; output Z; specify (PAD*> Z) = (1:1:1, 0:0:0); endspecify buf #(0.1) (Z, PAD); endmodule

endcelldefine //********************************************************//Copyright (c) AT&T Global Information Solutions 1994

timescale 100ps/10ps

celldefine module U0000000C1IC(A,ENB,PAD); input A, ENB; output PAD;specify (A *> PAD) = (12:12:12, 12:12:12) (ENB *> PAD) = (13:13:13,12:12:12); endspecify supply1 PWR; tri PAD; DELAY_BUF d1(ENB1_d,ENB);DELAY_BUF d2(ENB2_d,ENB); notif0 (strong1, highz0) (PADX, A, ENB1_d);notif0 (highz1, strong0) (PADX, A, ENB2_d); nmos (PAD, PADX, PWR);endmodule

endcelldefine //********************************************************//Copyright (c) AT&T Global Information Solutions 1954

timescale 100ps/10ps

celldefine module A00003100000(VDDIN,PAD) input VDDIN; output PAD;supply0 GND; supply1 PWR; pmos (A, PAD, GND); pmos (B, PAD, GND);pullup(A); pulldown(B); UDP_PPD_SLOWer (C_SLOW,A,B,PWR); UDP_PPD_FASTer(C_FAST,A,B,PWR); DELAY_BUF da0(CS0,C_SLOW); DELAY_BUF da1(CS1,CS0);DELAY_BUF da2(CS2,CS1); DELAY_BUF da3(CS3,CS2); DELAY_BUF da4(CS4,CS3);DELAY_BUF da5(CS5,CS4); DELAY_BUF da6(CS6,CS5); DELAY_BUF da7(CS7,CS6);DELAY_BUF da8(CS8,CS7); DELAY_BUF da9(C1,CS8); DELAY_BUF db0(C2,C_FAST);and (C12, C1, C2) rnmos (PAD,PWR,C12) rpmos (PAD,GND,GND); endmodule

endcelldefine /***************************************** //Copyright (c)AT&T Global Information Solutions 1994

timescale 100ps/10ps

celldefine module NCR_ISOLATE(A,X); input A; output X; supply0 GND;supply1 PWR; nmos (X, A, PWR); endmodule

endcelldefine //***************************************************//Copyright (c) AT&T Global Information Solutions 1954

timescale 100ps/10ps

celldefine module NCR_EXTERNAL,(VDDIN,PAD); input VDDIN; inout PAD;supply0 GND; supply1 PWR; reg NO_X; pmos (A, PAD, GND); pmos (B, PAD,GND); pmos (C, PAD, GND); pmos (D, PAD, GND); pullup(A); pulldown(B);nmos (C, GND, PWR); nmos (D, PWR, PWR) UDP_PPU_SLOWer (C_SLOW,PAD, A,B,C, D, GND,PWR); UDP_PPD_FASTer (C_FAST,PAD,A,B, C, D, GND,PWR);DELAY_BUF da0 (CS0,C_SLOW); DELAY_BUF da1 (CS1,CS0); DELAY_BUF da2(CS2,CS1); DELAY_BUF da3 (CS3,CS2); DELAY_BUF da4 (CS4,CS3); DELAY_BUFda5 (CS5,CS4); DELAY_BUF da6 (CS6,CS5); DELAY_BUF da7 (CS7,CS6);DELAY_BUF da8 (CS8,CS7); DELAY_BUF da9 (C1,CS8); DELAY_BUF db0(C2,C_FAST); and (C12, C1, C2); rnmos (PADX,GND,C12); rpmos(PADX,PWR,GND); nmos (PAD, PADX, EN); NCR_RACE rc1(EN); endmodule

endcelldefine /*************************************************//Copyright (c) AT&T Global Information Solutions 1994

timescale 100ps/10ps

celldefine module NCR_SWITCH(A, X); inout A; inout X; supply0 GND;supply1 PWR;

ifdef TESTER_EMULATION nmos (X, A, PWR);

else tran (X,A);

endif endmodule

endcelldefine

[0067] Writing to the output file will now be described. Referring toFIG. 11, it is seen that the logic simulation block 112 gets multipletypes of input information, and generates an output file 114. The actuallogic design itself is input from 108. Delay values 106, which are theresult of a delay calculator 104 such as Node5RC (available from AT&TMPD), are also input to the simulator 112. The delay values 106 arecalculated using parameters supplied by the simulation setup file 102known as simsetup, delay information contained in the cell & modellibrary 110, and the actual logic design 108. The simsetup file 102 alsoprovides information for use by the simulator. The actual stimulus to beapplied during simulation, and a list of nets/nodes to bemonitored/tracked, are specified in file 103. Finally, the detailedcells/models from library 110 (such as the VS500 library describedhereinabove) are input to the simulator, and provide the actualsimulation details for the particular logic design to be simulated.During simulation, the simulator outputs various values, including bothinput stimulus and resulting net/node values (both internal andexternal). These simulation results are stored in an output file 114 forsubsequent processing by other design test tools.

[0068] The system is able to instruct the simulator to log the internalsignals of the split I/O model through the use of the occurrence namefor each I/O pad cell (an occurrence name is a name for a node or netname that is internal to a model, as opposed to a regular node or netname that is external to a model). This requires that the occurrencename information be accessible for use by the simulator. In thepreferred embodiment, the occurrence name is stored in a Worksheetdatabase 103 of FIG. 11 (Worksheet is a design test tool available fromAT&T MPD that allows a user-friendly front end for specifying varioussimulator parameters in a manner that is independent of the particularsyntax/format of a particular simulator). Normally, the occurrence namewill be automatically extracted from the netlist when the Worksheetdatabase is initially created. In schematicless flows, the occurrencenames will be generated by Worksheet. In other cases, the user will needto enter the occurrence name information into the Worksheet database.

[0069] In summary, the split-I/O technique provides new modelingcapabilities. These capabilities include mid-cycle I/O (allowing inputstimulus to turn-on and turn-off at times other than cycle boundaries)and improved I/O contention handling. In previous versions of designtest tools, the information available in the simulation output files wasnot sufficient to allow these capabilities. The split-I/O techniqueprovides the design test tools with the extra information necessary tofully analyze the direction of the data present on the I/O signals. Thisallows users a greater flexibility in the types of waveforms they maygenerate during simulation.

[0070] The improved modeling of resistive states serves two purposes.First, it eliminates the incorrect design functionality that resultswhen inaccurate resistive states are used to control the input ofcircuitry. Second, it allows the design test tools to extract properstrobe placements for resistive signals. Without these changes, thepatterns produced by the design test tools which involve the strobing ofresistive states often result in test failures. These situations requiremanual—and often numerous—changes to correct the patterns. Since a largemajority of all designs utilize some type of pull resistors (internaland/or external), this is a significant issue in the effort to automatetest pattern development.

[0071] While we have illustrated and described the preferred embodimentsof our invention, it is to be understood that we do not limit ourselvesto the precise constructions herein disclosed, and the right is reservedto all changes and modifications coming within the scope of theinvention as defined in the appended claims.

We claim:
 1. A system for modeling a bi-directional signal of anelectric circuit, comprising: means for maintaining a state of an inputcomponent of the bi-directional signal; means for maintaining a state ofan output component of the bi-directional signal; and means forgenerating a resolved state based upon at least the input componentstate and output component state.
 2. The system of claim 1 wherein theresolved state is further based upon resistive data.
 3. The system ofclaim 1 wherein the input component state, output component state andresolved state are output to a computer file.
 4. An improved pad cellmodel, comprising: an input node which reflects data that is supplied tothe pad cell from external sources; an output node which reflects datathat is supplied as output from the pad cell; and a resolved node whichreflects the combination of the input node and output node.
 5. The padcell model of claim 4 wherein the resolved node also reflects thecombination of resistive data.
 6. The pad cell model of claim 4 furthercomprising means for selectively connecting the input node to theresolved node.
 7. An improved pad cell model, comprising: an I/O pad; anoutput driver; a buffer coupled between the I/O pad and the outputdriver; and an input receiver having an input and output, said inputreceiver comprising means for coupling the input (i) directly to theoutput, or (ii) to the output through a buffer.
 8. A method for modelinga bi-directional signal of an electric circuit, comprising the steps of:maintaining a state of an input component of the bi-directional signal;maintaining a state of an output component of the bi-directional signal;and generating a resolved state based upon at least the input componentstate and output component state.
 9. The method of claim 8 wherein theresolved state is further based upon resistive data.
 10. The method ofclaim 8 further comprising the steps of: specifying at least onebi-directional signal of a logic design to be simulated; and simulatingthe logic design.
 11. The method of claim 8 further comprising the stepof selecting whether to couple the input (i) directly to the output, or(ii) to the output through a buffer.
 12. A method for operating the padcell model of claim 4 in accordance with the method of claim 8.